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bus topology

网络  总线型; 总线型拓扑; 总线结构; 总线拓扑结构; 汇流排拓朴

计算机

英英释义

noun

  • the topology of a network whose components are connected by a busbar
      Synonym:bus

    双语例句

    • The stay and flow of token in Petri net is very like the storage and flow of information in avionics integrated network system, and bus system topology can be very well described with Petri net.
      由于Petri网中标记的驻留与流动和航空电子综合化网络系统中信息的存储与流动是及其相似的并且Petri网的网络结构能够直观、形象的表达总线系统的拓扑结构。
    • Since we'll create our bus topology with the administration console, that topology will use the single bus-wide default reply destination.
      由于我们要在管理控制台创建总线拓扑,因此该拓扑将使用一个总线范围内的缺省应答目的地。
    • This paper proposes an innovation graph method for the location and identification of the substation bus topology errors.
      提出了用新息图法辨识母线拓扑错误的方法。
    • The bus topology is composed of a single link connected to many computers.
      总线结构是有许多台计算机连接在单一的链接电路中。
    • After this we can treat with the coating and make it into HA coating. In the paper, the LIN bus is described and the CAN-LIN bus topology diagram is designed. Both the software and hardware are tested on a body test-bed at last.
      本文对LIN总线进行了介绍,设计了CAN-LIN总线网络拓扑结构图,并对CAN-LIN节点的软硬件进行了设计调试,最后连接车身电器试验台进行了测试。
    • For example, a hybrid topology could be the combination of a star and bus topology.
      例如,一个混合型拓扑结构和总线型拓扑结构的结合。
    • Focuses on the characteristics of the PCI Express bus, PCI Express bus-based system topology, services and equipment, such as the basic knowledge level. 2.
      重点介绍了PCIExpress总线特点、基于PCIExpress总线的系统拓扑结构、事务和设备层次等的基本知识。
    • The network operates on dual bus topology and the tunable transmitter and fixed receiver scheme to facilitate data multiaccess.
      网络拓扑采用环形,网络节点采用可调输出固定输入的选波原则以利于数据的多重接入。
    • Today, bus topology has been more and more popular in control network, while there are still several ways of media access control ( MAC).
      当前,在面向控制的局域网内,总线网络已经成为一种常见的拓扑结构;
    • The chip network can be realized in bus, ring, and star topology physically under the assumption.
      在假设条件下,芯片网络可采用总线型、环型或星型物理拓扑结构连接。